A UVM Register Model Based Tool Helps To Enhance Chip Designers’ Productivity

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IDesignSpec is one such innovative tool developed by Agnisys which helps to enhance the productivity of chip designers building IP/SoC designs. Based on UVM Register Model, this tool enables them to create a simple yet powerful specification in Excel, MS Word, Libre Office or plain text. It automates ASIC, SoC and FPGA specification to code generation.

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